B07465D4D3 EBOK by 2017

Author:2017
Language: eng
Format: epub
Published: 0101-01-01T00:00:00+00:00

The SystemVerilog code of the FPGA application that models the behavior of the multiplexer is shown in Listing 4.

Listing 4.

// implementing 4-channel mux

module mux2sel (clk_50M, // on-board clock of 50 MHz

sel,

muxout);

input clk_50M; // on-board clock of 50 MHz

input [1:0] sel; // mux select input

output muxout; // mux output

reg clk05s, clk1s, clk2s, clk5s; // internal nodes assigned to clock sources

parameter maxCNT05s = 12500000; // 2 Hz clock

parameter maxCNT1s = 25000000; // 1 Hz clock

parameter maxCNT2s = 50000000; // 0.5 Hz clock

parameter maxCNT5s = 125000000; // 0.2 Hz clock

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